Evaluation of NOC Using Tightly Coupled Router Architecture

One of the most important role in many core system is played by Network on Chip (NoC). Researchers are recently focusing on the design and optimization of NoC. In this paper we describe the architecture of a tightly coupled NoC router. To improve the network performance the router uses the on-chip storage and to improve the use of on-chip resource and information, several optimizations are introduced. In theory this design can save 9.3% chip area. The experiment shows that the latency can be reduced to 75% by the process of optimization on the ejection process and energy consumption by 31.5% in heavy traffic load network. Under different buffer depth, it can also improve latency by 20% and energy consumption by 25%. The experimentally results also prove that this tightly coupled router architecture can achieve better performance in the large scale network.